Power Sequencing, Intel® EP80579 Integrated Processor: Note
In the earlier days of Intel Architecture (IA), system designs for power sequence and reset circuitries were simpler and used fewer components to monitor power and power control signals. With fewer power rails, the power sequence was also less complicated. Currently, due to an increased need to support a variety of logic voltage levels—some being legacy, some being new lower levels for supporting higher speeds such as DDR, and some being high speed differentials—the number of required power rails has increased dramatically. These factors have caused the power sequence and reset to become far more complex. Therefore to bring a processor out of reset, the number of power monitors and sequences between supplies requires careful design to meet the specified timings required by the chip set or system-on-chip (SoC) devices.
Since there is currently no off-the-shelf power supply brick capable of generating the power sequence and all of the required power good signals, designers are required to design with discrete components. This requires a good understanding of how the power sequence and reset functions.
This document will help designers meet the required sequence and timing specified in the datasheet. There are also three main points of focus in this application note. The first one is to provide design considerations when implementing power sequence and reset for the Intel® EP80579 Integrated Processor with and without suspend power management. The second is to provide an alternative solution that can eliminate the Super I/O in designs that do not require additional peripherals supported by Super I/O and BOM cost reduction is important. The third point of point of focus in this document is to present relevant information and considerations for successfully bringing out of reset the processor.
Read the full Power Sequencing, Intel® EP80579 Integrated Processor Note.