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Intel® Platform Innovation Framework for EFI

Zip file: The following specifications for the Intel® Platform Innovation Framework for EFI are available for download

EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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Intel® Platform Innovation Framework for EFI—CSM Spec, Rev. 97

Revision 0.97: high-level design of the Compatibility Support Module code to implement the Intel® Platform Innovation Framework for EFI.

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EFI Driver Execution Environment Core Interface Spec v0.9

Specification: core code and services to implement the Driver Execution Environment (DXE) phase of the Intel® Platform Innovation Framework for EFI.

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EFI Hot-Plug PCI Initialization Protocol Specification v0.9

Hot-Plug PCI Initialization Protocol Specification for the Intel® Platform Innovation Framework for EFI defines the core code for implementation.

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EFI IDE Controller Initialization Protocol Specification v0.9

IDE Controller Initialization Protocol Specification for the Intel® Platform Innovation Framework for EFI defines core code implementation.

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EFI Memory Subclass Specification v0.9

Specification defines required core code and services for the memory data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI Pre-EFI Initialization Core Interface Specification v0.91

Defines core code for an implementation of the Pre-EFI Initialization phase of the Intel® Platform Innovation Framework for EFI.

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EFI Platform IDE Initialization Protocol Specification v0.3

Defines core code and services required of the platform IDE initialization protocol implementation in the Intel® Platform Innovation Framework.

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EFI Processor Subclass Specification v0.9

Defines core code for an implementation of the processor data hub subclass of the Intel® Platform Innovation Framework for EFI.

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